In this tutorial on FPGA programming using VHDL language, you will learn how to write VHDL code for 2 to 4 decoder and see the simulated waveform using VHDL software.
A decoder is used to decode encoded binary values to distinct values. If there n-bit binary message, then we can get upto 2n distinct decoded values. For example if we have n=2 bit messages like 00, 01, 10 and 11 then we can decode these to 0001, 0010, 0100 and 1000 using a decoder. Decoders are basic components in a digital system and they belong to combinational circuit class in digital system theory(see Combinational vs Sequential digital VHDL circuits). A table that shows the relationship between the input and outputs is called a truth table. The truth table for a 2 to 4 decoder is shown below.
The IEEE symbol for a 2 to 4 decoder is shown below.
We can implement such Decoders in VHDL language in various ways. In the following we use when..else statements to implement the 2 to 4 decoder. Below is VHDL code for 2 to 4 decoder.
entity decoder is
a : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0)
end entity decoder;
architecture decoderArch of decoder is
z <= "0001" when a = "00" else
"0010" when a = "01" else
"0100" when a = "10" else
"1000" when a = "11" else
end architecture decoderArch;
This form of writing VHDL code by simply minicing the behavior of component or system is called behavioral VHDL coding. Other ways of implementing a decoder is structural and data flow coding.
The following shows the simulated output of the above VHDL code using Active-HDL VHDL software.
Similarly, by constructing the input/output truth table for a 3 to 8 decoder, you can simply rewrite the above 2 to 4 decoder VHDL code to implement 3 to 8 decoder.
Decoders are one level higher digital components above and made up of basic logic gates. See vhdl code for logic gates to learn how to implement basic logic gates. See also What is Entity and Architecture in VHDL.