What is Entity and Architecture in VHDL

Entity and Architecture in VHDL language are VHDL language specific way of modeling a component or a digital system.

The entity can be small as a logic gate or large as a complete digital system. The entity declares the input and output signal names for the component or system that is being modeled. It is like sensors of the component or digital system that interacts with the externals of that entity. The externals can be another entity in a larger digital system or it can be any other external electronics or transducers. An entity must have at least one architecture.

The architecture of the entity encapsulates and defines the function of the entity, may contain definition of interconnected components(other entities) that makes up the very entity. In other words, the architecture body contains the internal description of the entity. The internal circuit could be combinational or sequential or both(see Combinational vs Sequential digital VHDL circuits)

entity and architecture


For example, an adder is entity. The inputs and outputs signals of the adder are entity declaration. The architecture will contain the functional logic of the adder- adding two input signals and outputting the signal. This functional logic can be constructed using basic logic gates inVHDL language which is one architecture or the same functional logic can be implemented using behavioral modeling paradigm. This then would be 2nd way of describing the adder and would constitute another architecture declaration. If there are multiple architectures for an entity then we use the configuration declaration to specify which architecture should be bind with the entity.

A simple Half Adder circuit is shown below.

The half adder has input signals A and B and the output signals are SUM and CARRY. These signal constitute the entity declaration for the half adder entity. Internally it is made up of an XOR gate X1 and an AND gate A1. The function of the adder would be described by interconnecting the gates. This would be the architecture for the adder.

Entity declaration VHDL code

Architecture declaration VHDL code

Half Adder Entity

When using VHDL software such as Xilinx or Active-HDL we can perform the analysis, synthesis and then perform simulation to check the functionality of the component. We can use such VHDL software to check the configuration for binding the entity and architecture.

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