A three state buffer or a tri-state buffer is a digital component used in digital circuit normally to disconnect a signal from a wire. It has an enable input which can be used to disconnect the input and output, thus stopping the signal flow. The IEEE symbol for a three-state buffer is as shown below.
The symbol ‘1’ is to indicate that the device is a buffer. The ‘EN’ is is input to enable output and the triangle indicates a three-state output. The output is disconnected it is normally in a high Impedance state. In VHDL language, the data type ‘Z’ is used for high impedance state.
Like D flip flop, three state buffers belongs to combinational digital circuit, see Combinational vs Sequential digital VHDL circuits. We can implement three state buffer in many ways with VHDL language. That is, we can describe the behavior of the three state buffer or we can use basic logic gates. Generally, implementing digital components more complex than three state buffers using basic logic gates can be tedious because we have to do analysis and synthesis to obtain the circuit that does do the logic function. That’s why it is more advantageous to utilize the available VHDL language behavioral language constructs.
So below is one example that shows how we can implement three state buffers using behavioral VHDL language. It uses When…else statement.
entity three_state_buffer is
a, EN : in std_logic;
z : out std_logic
end entity three_state_buffer;
architecture when_else of three_state_buffer is
z <= a when EN = '1' else 'Z';
end architecture when_else;
In the above code, when the enable input EN is high, the output z is the input a otherwise the output z is in high impedance state.
The above code can be simulated in any VHDL software such as Xilinx or Altera. Below is the simulation of the above three state buffer VHDL code in Active-HDL VHDL software.