In this tutorial, it is shown how to interface Intel 8086 microprocessor with memory chips using Proteus Professional ISIS schematic editor.
The Intel 8086 microprocessor has 20 address lines so it can read or write to 1MB memory location. The 1MB memory is segmented and is partitioned into two memory called bank 0 and bank 1. The bank 0 is also called even addressed bank and the bank 1 is also called odd addressed bank. When interfacing the 8086 must be connected to both even and odd addressed bank.
The following are steps to interface 8086 microprocessor to the memory 512KB EPROM and 512KB RAM in proteus.
First the 8086 microprocessor looks like the following in Proteus:
The AD0 to AD15 are address and data time multiplexed and so they must be demultiplexed to latch the address line A0 to A15. For this lines we need two 74LS373. The A16 to A19 are also multiplexed so we also need to demultiplex these signals using another 74LS373. So we need to three 74LS373 latches. How to connect these latches to the 8086 is shown below.
In other to increase the data(D0 to D15) signal strength so that they can reach farther distance across the PCB we can add transceiver buffer 74LS245. The 74LS245 takes in 8 input and buffers the signals and outputs those 8 input signals. So we need two of those transceiver because we have D0 to D15 data signals. So we connect the data lines from the microprocessor to the two transceiver as shown by the circuit schematic below. In that figure, the two upper chips are 744LS245 octal transceivers to which the AD0 to AD15 are connected to get data lines D0 to D15.
The same schematic is shown in closer view below,
Still closer view is shown below,
In the same figure we have not connected the CE and the AB/BA pins of the 74LS245. These needs to be connected to the 8086 microprocessor data enable (DE) which has pin number 26 and the data direction controller pin(DT/R) which has pin number 27. These two pins of the microprocessor is shown below in closer look.
The data transfer controller signal from pin DT/R controls the data transfer to and from from the microprocessor since data bus is a bidirectional bus. DT means Data Transmit and R indicates Data Receive. This pin should be connected to the AB/BA. Another pin is the DEN which stands for Data Enable which is active low which should be connected to the CE(Chip Enable which is also active low) pin of the 74LS245 bus buffer. So with this connection the new schematic showing demultiplexing and transceiver circuit for 8086 microprocessor is shown below,
So upto now we have demultiplexed the address lines and buffered the data lines. So we have address and data lines ready to be interfaced with memory or I/O devices. But since we are considering the memory interfacing we will only be connecting memory ICs which is be the next described.
Consider that we wanted to interface ROM and RAM to the intel 8086 chip. We know that 8086 requires odd and even addressed memory both for ROM and RAM since 8086 is a 16bit microprocessor. So if we consider ROM alone, we need two ROM- one for odd bank and one for even bank. Similarly if we consider RAM we need two RAM for odd and even memory bank. Next we need to choose memory capacity. If we consider 256KB for each memory chip then we need four 256 memory chips. Two are 256KB ROM and two are 256 RAM. The total memory would be 4x256KB=1024KB =1MB. So this is also the maximum memory interfacing problem.
Here we will use two ROMs- 27256 and two RAMs- 26256. These chips are shown below,
In the above picture, the first two chips are 27256 EPROMs and the 3rd and 4th are 62256 SRAMs. The first EPROM should be odd addressed or Bank1 ROM memory, the second EPROM should be even addressed or Bank 0 ROM memory, the third RAM should be odd addressed or Bank 1 RAM and the 4th should be even addressed or Bank 0 RAM.
The odd addresses EPROM and SRAM should be connected to the higher order data lines, that is, D8 to D15. The even addresses EPROM and SRAM should be connected to the lower order data lines, that is, D0 to D7. Each of these memory chips are selected by the BHE active low and the A0 address line pin of the 8086 microprocessor. This will be explained a little bit later.
The number of address lines required for these memory chip is 15. Since A0 address line is already required to select the memory chips, A1 to A15 will be connected to the memory chips. So the schematic showing the connection of the data lines and the address lines(A1 to A15) is shown below-
A more closer look to the memory chips is shown below-
Now we need to make connection to the chip select pin of each of the memory chips from the 8086 microprocessor via decoding logic.
For decoding circuit we can use the 74LS138 3×8 decoder chip. This chip was explained in earlier blog post and even VHDL code was developed for this decoder.
Here the solution for the decoder circuit is to use two 74LS138 decoder. One is for the remaining address lines A16 to A19 which has not yet been connected. And the other is for the read and write signal from the microprocessor.
The decoding logic for the address lines A16 to A19 is shown below,
In the figure above, A16, A17 and A18 are connected to the A, B and C of the 3 inputs of the decoder and the A19 pin is connected to the enable high pin of the decoder E1. E2 and E3 enable pin are grounded as required to activation of the decoder. The outputs of the decoder Y0 to Y7 have to be suitably connected to the chip select (CS) pin of the four memory chips.
Similarly, as shown by the figure below the read(RD), write(WR) and the M/IO can be connected to the 74LS138 decoder to get 4 signals for memory read, memory write, I/O read and I/O write.
In the above figure the output of the decoder Y0 to Y7 has to connected to the OE pin of the memory chips(both ROM and RAM) for memory read operation and to the WE pin of the two RAMs.
Before connecting the outputs of the two decoders to the respective places we have to make the decoder logic for the BHE and A0 pins. Remembering that the BHE is for odd addressed banks(ROM and RAM) and A0 is for even addressed memory banks(ROM and RAM) we make the decoding logic by connecting to the input of CS pin a 2-input OR gate 7432. This part of the decoding logic is shown below.
As the 1st(EPROM) and the 3rd(SRAM) memories are odd addressed memory chips, they are to be connected to the BHE signal from the microprocessor. The BHE signal was earlier connected to the octal transceiver and now the output from that transceiver will be connected to the 1st and 3rd memory chips via the OR gate. This connection is shown below.
Similarly A0 address line is for selection of the even addressed memory banks. So A0 is connected to the 2nd and the 3rd memory chips via the OR gates as shown below.
As you can see from the figure above, each of the OR gates needs another signal input. From the decoder logic that connected the address lines A16 to A18 we have not yet taken the output signal from the decoder. The output from that decoder should be connected appropriately to the free inputs of the OR gates.
We need to know the input and output signal relation which can be found from the 74LS138 decoder datasheet which is provided below.
We need A16, A17, A18 high for which case we have Y7 as the output signal that is connected to the ODD EPROM OR input gate for chip select. Next Y6 is selected and connected to the ODD SRAM OR gate input. Y0 is connected to the EVEN EPROM and Y1 is connected to the EVEN SRAM. This is shown below,
Thus the final memory chip interfacing circuit diagram is shown below,