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Basic Logic Gates with VHDL

How to implement Basic Logic Gates with VHDL programming language

In this tutorial you will learn how to implement Basic Logic Gates with VHDL programming language. Basic logic gates are AND, OR, NOR, XOR, NOT gates etc. They are the foundation building block of digital system. We can implement gates into FPGA devices using VHDL language and here we show the codes for them. First we have to write the gate code in VHDL and check the syntax, optionally simulate and verify the gate and upload to FPGA device. Normally this is done with FPGA program IDE(Integrated Development Environment) to write the code, compile and upload the code to the FPGA device. FPGA software are supplied normally by the FPGA vendors like Xilinx or Altera and others.

Any digital system that we implement with VHDL programming language consist of library import at the top, followed by the entity then an architecture. The entity is like head of a person, which has input and output port defined. The architecture is like the body of a person in which the processing of the input and output signal generation takes place. This will be understood with the examples below.

Suppose we want to implement AND gate in FPGA device using VHDL programming language. The first thing we need to do is to open the FPGA programming software like Xilinx ISE for Xilinx FPGA devices.

In the Xilinx ISE code editor window we write the VHDL code for AND gate. It looks like the following in Xilinx FPGA programming software.

On the right side you can see the code of the 2 input AND gate. On the left side you can see the project navigation panel, the various tools to check syntax, generate schematic and implementation tools among others.

The following is the two input AND gate VHDL code:

The next step is to check whether the written VHDL code is actually syntactically correct. There is a button on the right pane to check the syntax of the code.

After that we need to test the AND gate. There are two ways in doing this. Either you can write a testbench code or you can use the simulator tool to input signals and check the output. For small code like this one or small system VHDL code there is actually no need for testbench. That is because it is rather quicker with the simulator input signal tools. See You don’t need testbench all the time for more on this.

However we will show for illustration purpose how to write VHDL testbench code and simulate the AND gate with that. The simplest testbench VHDL code for 2-input AND gate is as follows.

With Xilinx Isim simulator we can then check the AND gate function with the above testbench code.

Launching Isim and you will see the digital waveform graph as shown below.

As you can see from the graph, when both inputs a and b are 0 then output z is also 0, when a=0 and b = 1 then the output z = 0, when a = 1, b = 0, then z = 0 and finally when both a and b are 1 then the output z is 1. Thus the AND gate VHDL code works as expected.

The next thing to do is to upload the AND gate VHDL to the FPGA device you are using. This can be done readily using Xilinx ISE software.

Next we show how to write VHDL code for OR basic logic gate.

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