While testbench code is without doubt necessary and essential for simulating large HDL design, it is often not necessary for small code design. As a beginner it is often useful to check your small Verilog or VHDL code using the simulator inbuilt signal specifier tool. Most of the HDL simulator like Xilinx Isim, Modelsim, Aldec Active HDL have inbuilt tool which allows you to specify signal at the time of simulation. This means you don’t need to specify the input signal for testing your code with testbench.
Let’s take an example. Suppose you were a beginner and wanted to test your small VHDL code like code for D flip flop. Suppose you are using Xilinx Isim simulator.
Once you have written your D flip flop and checked your syntax, fire up the Isim simulator. You should have something like the following screenshot.
Now, this is already simulated with some input to d and the output z. But this does not matter. You can always specify the input as well as clock signal.
First see how to specify the clock signal. Right click on your clock signal, here it’s clk. Then choose Force Clock as shown below.
Then define the clock such as the starting bit like 0 and then the trailing bit 1, the clock period like 10 ns. There is also an option to turn the clock off after some specific time period or turning on the clock after some particular time(default is 0 which means the start of simulation).
Click Apply then OK and you have created a clock signal. This is same clock as you would normally write in the testbench.
Similarly, you can specify the input signal high or low. For example in our case, the D fliop flop has input d. Now to specify its value just right click on the d signal in your waveform window and select Force Constant.
In this case we have specified input of 1(high). There are also option to specify when to start the input bit and when to turn it off as you can see in the above picture. Click Apply then OK. Now this is also the same input signal which you would write in your testbench code.
After you have specified what you wanted you can run the simulation.
Now whats the difference between using a testbench code and the simulator option to specify the inputs you might ask. Well, testbench is ofcourse more important and better ways or the standard way to test your HDL code but sometimes you just need not write the whole large testbench code. Testbench code can get quite large depending upon your HDL design. Thus for smaller design it is often more convenient to use the HDL simulator driving input facility. After all there are not just there. Moreover, even in many complicated or large designs, you may want to check out just some few inputs and outputs and how they are related or to verify the correctness of their signal propagation. Here too the simulator tool becomes handy.
Again, just to emphasize, you should learn how to write testbench for your code from the beginning because they are very important in FPGA design and simulation. This here is just to remind you or give tip that it is not necessary to write testbench for small design testing.