difference between Verilog and VHDL code for D flip flop

See the difference between D flip flop verilog and VHDL code

The following table shows the difference between Verilog Code and VHDL code for D flip flop. It shows in a comparative manner how they are differently written and helps beginners understand coding difference.

VerilogVHDL
module dff(
input D,
output reg Q,
output reg Qn,
input clk,
input rst
);

always @(posedge clk or negedge rst)
begin
if(rst == 1'b0)
begin
Q <= 0;
Qn <= 1;
end
else
begin
Q <= D;
Qn <= !D;
end
end

endmodule
library ieee;
use ieee.std_logic_1164.all;

entity dff is
port(
D,clk : in std_logic;
Q,Qn : inout std_logic
);
end dff;

architecture behave of dff is
signal S : std_logic;
begin
process(D,clk)
begin
if clk'event and clk = '1' then
S <= D;
end if;
end process;

Q <= S;
Qn <= not S;
end behave;

 

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