D flip flop Verilog code with testbench

Fully tested code in Xilinx Isim and Modelsim simulators

D flip flop verilog code is written along with the required testbench code. The codes are written and simulated in Xilinx ISE design suite. And then the same D flip flop verilog code was tested in Modelsim simulator to verify the code.

Verilog D Flip flop Code

Below is the verilog code for D flip flip.

Testbench Code

The testbench code for the above D flip flop code:

Simulation

The simulation waveform is shown below.

D flip flop Verilog code
Fig: d flip flop simulation in Xilinx Isim

The same above code was tested in Modelsim. Below is the simulation waveform.

modelsim d flip flop testing

 

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